The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Jan. 20, 2017
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Martin Kessler, Salem, MA (US);

William Hooper, Newton, MA (US);

Lewis F. Lahr, Dover, MA (US);

Assignee:

ANALOG DEVICES, INC., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/364 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01);
Abstract

Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.


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