The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

May. 29, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Thomas Anton Leyrer, Geisenhausen, DE;

William Cronin Wallace, Richardson, TX (US);

David Alston Lide, Rockville, MD (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H04L 1/00 (2006.01); G06F 9/448 (2018.01); G06F 9/48 (2006.01); G06F 16/9035 (2019.01); G06F 9/52 (2006.01); G06F 9/50 (2006.01); G06F 1/06 (2006.01); G06F 13/20 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 1/06 (2013.01); G06F 9/448 (2018.02); G06F 9/5011 (2013.01); G06F 9/5016 (2013.01); G06F 9/5038 (2013.01); G06F 9/52 (2013.01); G06F 11/1004 (2013.01); G06F 13/20 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01); G06F 16/9035 (2019.01); H04L 1/0041 (2013.01); G06F 2209/503 (2013.01); G06F 2209/5012 (2013.01);
Abstract

A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.


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