The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Mar. 08, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Do-Sun Hong, Gyeonggi-do, KR;

Dong-Gun Kim, Gyeonggi-do, KR;

Yong-Ju Kim, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0616 (2013.01); G06F 3/0631 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/10 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/202 (2013.01); G06F 2212/657 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.


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