The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Jul. 02, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Whee-Won Lee, Busan, KR;

Ga-Na Kim, Icheon-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/13 (2006.01); G02F 1/1362 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G09G 3/20 (2006.01); G02F 1/133 (2006.01); G09G 3/3208 (2016.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/133 (2013.01); G09G 3/20 (2013.01); G09G 3/3208 (2013.01); G09G 3/3266 (2013.01); G09G 3/36 (2013.01); G09G 3/3607 (2013.01); G09G 3/3677 (2013.01); G09G 3/3611 (2013.01); G09G 2300/0408 (2013.01); G09G 2320/0223 (2013.01);
Abstract

A display device includes: pixels; gate lines for connecting to the pixels; a first gate driving block for connecting to first and second gate lines that are adjacent to each other; and a second gate driving block for connecting to the first gate line and the second gate line, wherein the first gate driving block includes: a first gate signal generating portion; a first transistor connected between a first output terminal of the first gate signal generating portion and the first gate line; and a second transistor connected between the first output terminal and the second gate line, wherein the second gate driving block includes: a second gate signal generating portion; a third transistor connected between a second output terminal of the second gate signal generating portion and the first gate line; and a fourth transistor connected between the second output terminal and the second gate line.


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