The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Oct. 05, 2017
Applicant:

Sumitomo Electric Printed Circuits, Inc., Koka, JP;

Inventors:

Kohei Okamoto, Koka, JP;

Yoshihito Yamaguchi, Koka, JP;

Kousuke Miura, Koka, JP;

Hiroshi Ueda, Koka, JP;

Atsushi Kimura, Koka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/46 (2006.01); H05K 3/28 (2006.01); H05K 1/11 (2006.01); H05K 3/06 (2006.01); H05K 1/03 (2006.01); H01F 17/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H01F 17/00 (2013.01); H05K 1/0393 (2013.01); H05K 1/118 (2013.01); H05K 3/06 (2013.01); H05K 3/281 (2013.01); H05K 3/4644 (2013.01); H05K 2201/0141 (2013.01); H05K 2201/0145 (2013.01); H05K 2201/0154 (2013.01); H05K 2203/066 (2013.01);
Abstract

A printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, a conductive pattern that is stacked on at least one surface side of the base film and that includes a plurality of wiring portions arranged adjacent to one another, and an insulating layer that covers outer surfaces of the base film and the conductive pattern. The plurality of wiring portions have an average spacing of 1 μm or more and 20 μm or less and an average height of 30 μm or more and 120 μm or less. A filling area ratio of the insulating layer between the plurality of wiring portions adjacent to one another in sectional view is 95% or more.


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