The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Nov. 30, 2018
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Sebastien Gareau, Ottawa, CA;

Daniel Claude Perras, Ottawa, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H04J 3/06 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H04J 3/0658 (2013.01);
Abstract

Virtualized Synchronous Ethernet systems and methods include, in a network element supporting a plurality of slices over a common Ethernet physical (PHY) connection, determining a common PHY frequency; for a specific slice of the plurality of slices, obtaining a bit-level accurate count (C) over a accumulation window; and determining a client clock for the specific slice based on the common PHY frequency and the bit-level accurate count (C). The systems and methods can include receiving the bit-level accurate count (C) from a second network element for synchronization therewith. The bit-level accurate count (C) over the given accumulation window can be determined utilizing accumulators and the client clock can be determined utilizing Digital Phase Lock Loops (DPLLs).


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