The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Nov. 17, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Wonhyun Choi, Gunpo-si, KR;

Minsu Kim, Hwaseong-si, KR;

Sungyong Kim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/58 (2006.01); H03K 23/40 (2006.01); H03M 7/16 (2006.01);
U.S. Cl.
CPC ...
H03K 23/588 (2013.01); H03K 23/40 (2013.01); H03M 7/16 (2013.01);
Abstract

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.


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