The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Apr. 10, 2020
Applicant:

The Research Foundation for the State University of New York, Albany, NY (US);

Inventors:

Amirhossein Goldan, Stony Brook, NY (US);

Wei Zhao, East Setauket, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/06 (2006.01); H01L 31/0272 (2006.01); H01L 31/107 (2006.01); H01L 27/146 (2006.01); H01L 31/0352 (2006.01); H01L 31/0216 (2014.01); H01L 31/0224 (2006.01); H01L 31/0376 (2006.01); H01L 31/105 (2006.01);
U.S. Cl.
CPC ...
H01L 31/0272 (2013.01); H01L 27/1461 (2013.01); H01L 27/1463 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14659 (2013.01); H01L 27/14696 (2013.01); H01L 31/02161 (2013.01); H01L 31/022408 (2013.01); H01L 31/0376 (2013.01); H01L 31/035209 (2013.01); H01L 31/105 (2013.01); H01L 31/107 (2013.01); H01L 27/14612 (2013.01); H01L 27/14632 (2013.01); H01L 27/14692 (2013.01);
Abstract

Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se.


Find Patent Forward Citations

Loading…