The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Mar. 25, 2019
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Wen-Yueh Jang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7923 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/66833 (2013.01);
Abstract

A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.


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