The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jun. 02, 2017
Applicant:

Seoul National University R&db Foundation, Seoul, KR;

Inventors:

Jong-Ho Lee, Seoul, KR;

Sung Yun Woo, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/749 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01); H01L 27/102 (2006.01); H01L 29/51 (2006.01); H01L 29/74 (2006.01); H01L 29/792 (2006.01); H03K 3/012 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/749 (2013.01); G06N 3/049 (2013.01); G06N 3/0445 (2013.01); G06N 3/0635 (2013.01); H01L 27/1027 (2013.01); H01L 29/40117 (2019.08); H01L 29/42308 (2013.01); H01L 29/42344 (2013.01); H01L 29/513 (2013.01); H01L 29/66833 (2013.01); H01L 29/7436 (2013.01); H01L 29/792 (2013.01); H03K 3/012 (2013.01); H01L 29/7855 (2013.01);
Abstract

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.


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