The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Dec. 26, 2018
Applicant:

X-fab France, Corbeil Essonnes, FR;

Inventor:

Nicolas Pons, Draveil, FR;

Assignee:

X-FAB FRANCE, Corbeil Essonnes, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/28123 (2013.01); H01L 21/76283 (2013.01); H01L 27/127 (2013.01); H01L 27/1296 (2013.01); H01L 29/42372 (2013.01); H01L 29/78654 (2013.01);
Abstract

A method of forming a transistor from a stack of layers comprising at least one insulating layer topped by at least one active layer and at least one first and one second insulating trench defining in the active layer a reception area for receiving the transistor, the transistor comprising a conduction channel formed at least partially in the active layer, the method comprising at least the following steps: forming a grid stack extending over at least the conduction channel; forming a source zone and a drain zone; wherein the formation of the grid stack is carried out in such a way as to provide at least a first and a second portion of the reception zone, not covered by the grid stack.


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