The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jul. 09, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seok Cheon Baek, Hwaseong-si, KR;

Young Woo Kim, Hwaseong-si, KR;

Dong Sik Lee, Osan-si, KR;

Min Yong Lee, Incheon, KR;

Woong Seop Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 27/11556 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/0649 (2013.01);
Abstract

A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.


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