The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jul. 03, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Fumitaka Arai, Mie, JP;

Masakazu Goto, Mie, JP;

Masaki Kondo, Mie, JP;

Keiji Hosotani, Mie, JP;

Nobuyuki Momo, Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); G11C 11/5621 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.


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