The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Nov. 30, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Donald William Kidwell, Jr., Los Gatos, CA (US);

Ravindra Vaman Shenoy, Dublin, CA (US);

Alan Lewis, Sunnyvale, CA (US);

Christopher Feuling Ferguson, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/24 (2006.01); H01F 27/28 (2006.01); H01F 41/04 (2006.01); H01F 41/12 (2006.01); H01L 23/64 (2006.01); H01F 27/32 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01F 17/00 (2006.01);
U.S. Cl.
CPC ...
H01F 27/2804 (2013.01); H01F 17/0033 (2013.01); H01F 27/24 (2013.01); H01F 27/323 (2013.01); H01F 41/041 (2013.01); H01F 41/046 (2013.01); H01F 41/122 (2013.01); H01L 23/5227 (2013.01); H01L 23/645 (2013.01); H01L 28/10 (2013.01); H01F 2027/2809 (2013.01); H01L 2924/1206 (2013.01);
Abstract

Some aspects pertain to an inductor apparatus that includes a first metal layer including a plurality of first interconnects, a second metal including a plurality of second interconnects, a first dielectric layer between the first metal layer and the second metal layer, and an inductor. The inductor includes a plurality of vias, where the plurality of vias are configured to couple the plurality of first interconnects to the plurality of second interconnects. The inductor includes a plurality of inductor loops formed by the plurality of vias, the plurality of first interconnects and the plurality of second interconnects. The inductor further includes a first magnetic layer and a second magnetic layer, located between the first interconnects and the second interconnects; and a third magnetic layer and an optional fourth magnetic layer outside of the plurality of inductor loops.


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