The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Aug. 12, 2019
Applicant:

Arm Finance Overseas Limited, Cambridge, GB;

Inventors:

Soumya Banerjee, San Jose, CA (US);

Todd Michael Bezenek, San Jose, CA (US);

Clement Tse, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06Q 30/06 (2012.01); G06F 30/30 (2020.01); G06Q 50/18 (2012.01);
U.S. Cl.
CPC ...
G06Q 30/0621 (2013.01); G06F 30/30 (2020.01); G06Q 30/0609 (2013.01); G06Q 50/184 (2013.01);
Abstract

Systems and methods for using logic design processing to create an integrated circuit (IC). A method for creating an IC with a client device that is configured to perform all of the steps of receiving technology options and operating system options for the IC, selecting one of the technology options and one of the operating system options, receiving a subset of processor cores matching the selected technology option and the selected operating system option, identifying a particular processor core from among the subset of processor cores, customizing the particular processor core by adjusting at least one of default values for a system clock, a memory configuration, or a cache value based on the selected technology option to create a customized processor core configuration, presenting the customized processor core configuration in a graphical format and, in response, confirming the customized processor core configuration as a desired core configuration to be built, and sending device instructions to build an IC based on the desired core configuration.


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