Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory address

Abstract

A processing system includes a processing pipeline which includes fetch circuitry for fetching instructions to be executed from a memory. Buffer control circuitry is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffers fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.