The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2020
Filed:
Apr. 02, 2019
Applicant:
Google Llc, Mountain View, CA (US);
Inventors:
Monish Shah, Dublin, CA (US);
Benjamin Charles Serebrin, Sunnyvale, CA (US);
Albert Borchers, Aptos, CA (US);
Assignee:
Google LLC, Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/08 (2016.01); G06F 12/1081 (2016.01); G06F 12/0868 (2016.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0647 (2013.01); G06F 3/0611 (2013.01); G06F 3/0656 (2013.01); G06F 3/0685 (2013.01); G06F 12/08 (2013.01); G06F 12/1081 (2013.01); G06F 12/0868 (2013.01); G06F 13/28 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/312 (2013.01);
Abstract
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.