The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jun. 26, 2019
Applicant:

Ali Ghiasi, Cupertino, CA (US);

Inventor:

Ali Ghiasi, Cupertino, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); H01L 23/00 (2006.01); H04B 10/40 (2013.01); G02B 6/43 (2006.01); H04B 10/516 (2013.01); H04B 10/25 (2013.01);
U.S. Cl.
CPC ...
G02B 6/4284 (2013.01); G02B 6/425 (2013.01); G02B 6/4246 (2013.01); G02B 6/4272 (2013.01); G02B 6/4292 (2013.01); G02B 6/43 (2013.01); H01L 24/04 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H04B 10/40 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H04B 10/25 (2013.01); H04B 10/516 (2013.01);
Abstract

A method and system of co-packaging optoelectronics components or photonic integrated circuit (PIC) with application specific integrated circuits (ASICs) are disclosed and may include package substrate, several electronics die, passive components, socket assembly, and heat sinks. The said method converts ASIC high speed signals to optical signals by eliminating intermediary electrical interface between the ASIC and conventional optical modules. The method described provides many advantages of pluggable optical modules such as configurability, serviceability, and thermal isolation from the ASIC heat, while eliminating bandwidth bottlenecks as result of the ASIC package, host or linecard printed circuit board (PCB) traces, and the optical module connector. The high-power consumption ASIC is mounted below the package substrate, but sensitive optoelectronics and PIC components are mounted on top of the package substrate assembly for thermal isolation and serviceability. The package assembly ball grid array (BGA) or pin grid array (PGA) contacts are on the same side of the package substrate surface as ASIC die. The co-packaged package assembly is attached to the host or linecard PCB having a cutout for ASIC with the heatsink mounted from the bottom onto the ASIC die.


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