The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10863628 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 08, 2020

Filed:

Oct. 17, 2019
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

Matthew Twarog, Hubbardston, MA (US);

Hui He, San Jose, CA (US);

Thomas W. Jetton, Sunnyvale, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01); H05K 3/40 (2006.01); H05K 3/22 (2006.01);
U.S. Cl.
CPC ...
H05K 3/0047 (2013.01); H05K 1/0245 (2013.01); H05K 1/0251 (2013.01); H05K 1/115 (2013.01); H05K 3/225 (2013.01); H05K 3/4038 (2013.01); H05K 3/46 (2013.01); H05K 1/0243 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09609 (2013.01); H05K 2203/0207 (2013.01);
Abstract

A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.


Find Patent Forward Citations

Twarog, Matthew. (2020). Clearance size reduction for backdrilled differential vias (U.S. Patent No. 10863628). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10863628

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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