The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Dec. 26, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Marius Moe, Fetsund, NO;

Tarjei Aaberge, Oslo, NO;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H03L 7/081 (2006.01); H03K 5/14 (2014.01); H03K 3/03 (2006.01); H03K 5/00 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); H03K 3/0315 (2013.01); H03K 5/14 (2013.01); H03L 7/0812 (2013.01); G04F 10/005 (2013.01); H03K 2005/00019 (2013.01);
Abstract

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.


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