The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Apr. 26, 2019
Applicant:
Renesas Electronics America Inc., Milpitas, CA (US);
Inventor:
Shengling Deng, Chandler, AZ (US);
Assignee:
Renesas Electronics America Inc., Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7806 (2013.01);
Abstract
The present embodiments provide a region of a semiconductor device comprising a plurality of power transistor cells configured as trench MOSFETs in a semiconductor substrate. At least one active power transistor cell further includes a trenched source region wherein a trench bottom surface of the trenched source contact is covered with an insulation layer and layer of a conductive material on top of the insulation layer, to function as an integrated pseudo Schottky barrier diode in the active power transistor cell.