The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Mar. 14, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Akihiro Tobioka, Nagoya, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/461 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 21/311 (2006.01); H01L 21/033 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/11526 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01);
Abstract

An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.


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