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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10861865 B1

PDFFull Text
Date of Patent:
Dec. 08, 2020

Filed:

Sep. 05, 2019

Semiconductor storage device

Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yoshiaki Takahashi, Yokohama, JP;

Takahiro Tsurudo, Yokohama, JP;

Kiyofumi Sakurai, Yokohama, JP;

Assignee:

Toshiba Memory Corporation, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Pho M Luu

Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11573 (2017.01); H01L 27/11556 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/11526 (2017.01); G11C 16/24 (2006.01); G11C 11/56 (2006.01); H01L 27/11548 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

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