The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Oct. 15, 2018
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventor:

Tatsuo Tonedachi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/373 (2006.01); H01L 23/24 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 23/057 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/057 (2013.01); H01L 23/24 (2013.01); H01L 23/3735 (2013.01); H01L 23/5385 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 23/49861 (2013.01); H01L 24/45 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/29239 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/12031 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14252 (2013.01);
Abstract

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.


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