The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Nov. 30, 2018
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventor:
Su Hae Woo, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/1068 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01);
Abstract
A test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. The built-in repair analysis (BIRA) circuit receives the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. The repair target memory package is selected by considering an error correction capability of an error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages.