The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Oct. 28, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Rajiv Kumar Sisodia, Bangalore, IN;

Renu Rawat, Bangalore, IN;

Paul Darren Hoxey, Cambridge, GB;

Vikash, Bangalore, IN;

Kumaraswamy Ramanathan, Austin, TX (US);

Sanjay Mangal, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 7/10 (2006.01); G11C 29/32 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 7/1018 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/12015 (2013.01); G11C 29/32 (2013.01); G11C 5/066 (2013.01); G11C 7/1036 (2013.01); G11C 2029/1204 (2013.01); G11C 2207/107 (2013.01);
Abstract

A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.


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