The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Mar. 28, 2019
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Milam Paraschou, Dellwood, MN (US);

Jeffrey Cooper, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 15/04 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 15/04 (2013.01); G11C 2207/063 (2013.01);
Abstract

Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.


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