The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
May. 23, 2019
Xilinx, Inc., San Jose, CA (US);
Mukund Sivaraman, Palo Alto, CA (US);
Shail Aditya Gupta, San Jose, CA (US);
Akella Sastry, San Jose, CA (US);
Rishi Surendran, San Jose, CA (US);
Philip B. James-Roxby, Longmont, CO (US);
Samuel R. Bayliss, Mountain View, CA (US);
Vinod K. Kathail, Palo Alto, CA (US);
Ajit K. Agarwal, Hyderabad, IN;
Ralph D. Wittig, Menlo Park, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.