The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Oct. 30, 2019
Realtek Semiconductor Corp., HsinChu, TW;
Chien-Cheng Liu, Hsinchu County, TW;
Shih-Chih Liu, Hsinchu County, TW;
Yun-Chih Chang, Hsinchu County, TW;
Shu-Yi Kao, Hsinchu County, TW;
Realtek Semiconductor Corp., HsinChu, TW;
Abstract
A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).