The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Sep. 15, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andreas Hansson, Cambridge, GB;

Nikos Nikoleris, Cambridge, GB;

Wendy Arnott Elsasser, Austin, TX (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/0895 (2016.01); G06F 12/0864 (2016.01); G11C 11/16 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0895 (2013.01); G06F 12/0864 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/40622 (2013.01);
Abstract

Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.


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