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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10860252 B1

PDFFull Text
Date of Patent:
Dec. 08, 2020

Filed:

Mar. 14, 2019

Memory apparatus and methods with heterogeneous memory array architecture

Applicant:

Research & Business Foundation Sungkyunkwan University, Suwon-si, KR;

Inventors:

Joon Sung Yang, Suwon-si, KR;

Tae Hyun Kwon, Suwon-si, KR;

Imran Muhammad, Suwon-si, KR;

Jung Min You, Suwon-si, KR;

Assignee:

Research & Business Foundation Sungkyunkwan University, Suwon-si, KR;

Attorney:

NSIP Law

Primary Examiner:

Sean D Rossiter

Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 29/52 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0688 (2013.01); G06F 11/1068 (2013.01); G11C 11/5628 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/52 (2013.01);
Abstract

The present invention relates to memory apparatuses and an operating methods using a heterogeneous memory array. An operation method of a memory apparatus using a heterogeneous memory array according to an embodiment of the present invention includes dividing an input bit into at least one data bit according to a mode bit, and writing the divided data bits in each cell of the memory array by using a cell level of the memory array which is configured according to the mode bit.

Find Patent Forward Citations

Yang, Joon. (2020). Memory apparatus and methods with heterogeneous memory array architecture (U.S. Patent No. 10860252). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10860252

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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