The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Apr. 15, 2016
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventor:
Masashi Nagasato, Kyoto, JP;
Assignee:
Rohm Co., Ltd., Kyoto, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0243 (2013.01); H05K 1/025 (2013.01); H05K 3/4685 (2013.01); H05K 1/0242 (2013.01); H05K 2201/09154 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/09618 (2013.01); H05K 2201/09727 (2013.01); H05K 2201/09736 (2013.01); H05K 2201/1009 (2013.01); H05K 2201/10053 (2013.01); H05K 2201/10704 (2013.01); H05K 2201/10719 (2013.01); H05K 2201/10734 (2013.01);
Abstract
A printed wiring board used to suppress parasitic component is provided. The printed wiring boardincludes a multi-layer substrate, and a power linelaid on the multi-layer substrateand connected with a power terminal row T-Tof a semiconductor device. The power lineincludes a first wiring patternformed on a surface of the multi-layer substrate, a second wiring patternformed within the multi-layer substrate, and interlayer connectionsandelectrically conducting the first wiring patternand the second wiring patternto bypass at least a portion of the power terminal row T-T