The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

May. 31, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Shuing Ju, Santa Clara, CA (US);

Wenxiao Tan, Plano, TX (US);

Arun Rao, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 4/48 (2006.01);
U.S. Cl.
CPC ...
H03K 4/48 (2013.01);
Abstract

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.


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