The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Oct. 30, 2018
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Jianan Yang, Austin, TX (US);

James Nissen, Austin, TX (US);

David Wade Eickbusch, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356182 (2013.01); H03K 3/356113 (2013.01); H03K 19/018521 (2013.01);
Abstract

Level-shifting circuits including a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices may be used to level-shift an input voltage signal between a low voltage domain having a low voltage level and a high voltage domain having a high voltage level, to obtain an output voltage signal having an output voltage level at an output node. A current-controlled tie circuit may be connected between the output node and the output voltage level, to conduct a current that causes the output node of the level-shifting circuit to be in a pre-defined logic state during a power-up sequence of the level-shifting circuit. Accordingly, spurious, non-deterministic output levels are avoided during the power-up sequence.


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