The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jan. 31, 2019
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Fei Guo, Nanjing, CN;

Yihui Li, San Jose, CA (US);

Hong Xue, Shanghai, CN;

Xin Ma, San Jose, CA (US);

Hui Wang, Pleasanton, CA (US);

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/28 (2006.01); H04B 1/04 (2006.01); H03K 5/24 (2006.01);
U.S. Cl.
CPC ...
H03H 11/28 (2013.01); H03K 5/24 (2013.01); H04B 1/04 (2013.01);
Abstract

Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.


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