The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Jun. 20, 2019
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Digh Hisamoto, Tokyo, JP;
Yoshiyuki Kawashima, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/31144 (2013.01); H01L 21/762 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/66795 (2013.01);
Abstract
A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.