The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jan. 18, 2019
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Shunsuke Isono, Osaka, JP;

Hidenari Kanehara, Kyoto, JP;

Sanshiro Shishido, Osaka, JP;

Takeyoshi Tokuhara, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/30 (2006.01); H04N 5/374 (2011.01); H04N 5/376 (2011.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/307 (2013.01); H01L 27/14605 (2013.01); H01L 27/14607 (2013.01); H01L 27/14636 (2013.01); H01L 27/14665 (2013.01); H04N 5/374 (2013.01); H04N 5/376 (2013.01); H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01);
Abstract

An imaging device includes: a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region; an insulating layer that covers the pixel region and the peripheral region; a first electrode located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrode; a second electrode that covers the photoelectric conversion layer; detection circuitry located in the pixel region and connected to the first electrode; peripheral circuitry located in the peripheral region and connected to the detection circuitry; and a third electrode located on the insulating layer above the peripheral region. The second electrode extends above the peripheral region, and the second electrode includes a connection region in which the second electrode is connected to the third electrode, the connection region overlapping the peripheral circuitry in plan view.


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