The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Apr. 15, 2019
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Masakatsu Tominaga, Sakai, JP;

Masahiro Yoshida, Sakai, JP;

Yasuhiro Mimura, Sakai, JP;

Akane Sugisaka, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/02 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/136204 (2013.01); H01L 27/0255 (2013.01); H01L 27/1225 (2013.01);
Abstract

Provided is an active matrix substrate that includes a thin film transistor that has a first semiconductor layer and an ESD protection circuit. The ESD protection circuit includes a diode element. The diode element has a first electrode in a gate metal layer, a second semiconductor layer that overlaps a first electrode, and a second electrode and a third electrode electrically connected to a second semiconductor layer in a source metal layer. First and second electrodes of the diode element are electrically connected. The ESD protection circuit further includes a reserve diode structure. The reserve diode structure includes a fourth electrode in the gate metal layer and is in an electrically floating state, and a third semiconductor layer that is formed in the same layer as the first and second semiconductor layers and overlaps the fourth electrode with an insulation layer in between.


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