The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Nov. 29, 2019
Berex Corporation, Seoul, KR;
Oleksandr Gorbachov, Irvine, CA (US);
Lisette L. Zhang, Redondo Beach, CA (US);
Stephen Milkovits, Garden Grove, CA (US);
BeRex, Inc., Santa Clara, CA (US);
Abstract
An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.