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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10854455 B1

PDFFull Text
Date of Patent:
Dec. 01, 2020

Filed:

Nov. 20, 2017

Methods and apparatus for fabricating ic chips with tilted patterning

Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Runzi Chang, San Jose, CA (US);

Winston Lee, Palo Alto, CA (US);

Assignee:

Marvell Asia PTE, Ltd., Singapore, SG;

Attorney:
Primary Examiner:

Charles D Garber

Assistant Examiner:

S M Sohel Imtiaz

Int. Cl.
CPC ...
H01L 21/26 (2006.01); H01L 21/265 (2006.01); G03F 7/20 (2006.01); H01L 21/3213 (2006.01); G03F 7/11 (2006.01); H01L 21/027 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26586 (2013.01); G03F 7/11 (2013.01); G03F 7/201 (2013.01); H01L 21/0274 (2013.01); H01L 21/0276 (2013.01); H01L 21/02126 (2013.01); H01L 21/3086 (2013.01); H01L 21/31055 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/56 (2013.01); H01L 24/06 (2013.01);
Abstract

The present disclosure describes methods and apparatuses for fabricating integrated-circuit (IC) die with tilted patterning. In some aspects, mandrels are fabricated on a material stack and occlude portions of a layer of material from a field of energy radiated at an angle of incidence relative to the mandrels. The occluded portions of the layer of material can be used to mask an underlying film to create a film pattern on a substrate of the IC die. These methods and apparatuses may enable the fabrication of IC die with features that are smaller in size than those afforded by conventional lithography processes.

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