The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Dec. 20, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin Ho Kim, Hwaseongsi, KR;

Jeong Hwan Kim, Hwaseong-si, KR;

Sang Hyun Sung, Cheongju-si, KR;

Sung Lae Oh, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11565 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.


Find Patent Forward Citations

Loading…