The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Nov. 12, 2019
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Sukenori Ito, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/00 (2006.01); H01L 23/00 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/006 (2013.01); G09G 3/36 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); G09G 2320/043 (2013.01); G09G 2330/12 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01);
Abstract

The present disclosure relates to evaluation of a mounted resistor formed between a bump and electrodes. A display device of the present disclosure includes a display panel formed in a transparent substrate and a display driver driving the display panel. A plurality of bumps is formed on a connection surface of the display driver. A plurality of electrodes is formed on the transparent substrate and corresponds in position to the plurality of bumps. COG mounting enables the bumps on the display driver side to electrically connect to the electrodes on the transparent substrate side. On the connection surface of the display driver, the bumps, which are for use in signal transmission, further include a first evaluation-oriented bump (TA[i]) and a second evaluation-oriented bump (TB[i]). Evaluation-oriented electrodes (EL[i]) are disposed on the transparent substrate and correspond in position to the first evaluation-oriented bump (TA[i]) and the second evaluation-oriented bump (TB[i]). Upon completion of COG mounting, a resistance value evaluation circuit () disposed on the display driver generates evaluation signal (DET[i]) corresponding to resistance value (RA[i]+RB[i]) between the evaluation-oriented electrodes and the first and second evaluation-oriented bumps.


Find Patent Forward Citations

Ito, Sukenori. (2020). Semiconductor device, display driver and display device (U.S. Patent No. 10854122). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10854122

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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