The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Mar. 28, 2019
Applicant:
Provino Technologies, Inc., Santa Clara, CA (US);
Inventors:
Shailendra Desai, Ahmedabad, IN;
Mark Pearce, San Francisco, CA (US);
Amit Jain, Ahmedabad, IN;
Rutul Bhatt, Ahmedabad, IN;
Assignee:
PROVINO TECHNOLOGIES, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 13/362 (2006.01); G06F 13/366 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/20 (2013.01); G06F 9/466 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 13/366 (2013.01); G06F 13/3625 (2013.01); G06F 13/4022 (2013.01); G06F 15/7807 (2013.01); G06F 2213/0024 (2013.01); G06F 2213/0062 (2013.01);
Abstract
Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.