The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Apr. 18, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Somdutt Javre, Seoni, IN;

Siddharth Rele, Navi Mumbai, IN;

Gangadhar Budde, Renapur, IN;

Appa Rao Nali, Hyderabad, IN;

Chaitanya Kamarapu, Hyderabad, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 8/20 (2018.01); G06F 9/4401 (2018.01); G06F 8/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/50 (2013.01); G06F 8/20 (2013.01); G06F 8/30 (2013.01); G06F 9/4405 (2013.01); G06F 9/4406 (2013.01);
Abstract

Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.


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