The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Oct. 25, 2018
Applicant:

Dell Products, L.p., Round Rock, TX (US);

Inventors:

Johan Rahardjo, Austin, TX (US);

Pavan Kumar Gavvala, Anantapur, IN;

Assignee:

Dell Products, L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/76 (2013.01); G01R 31/317 (2006.01); G06F 21/30 (2013.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31719 (2013.01); G01R 31/3177 (2013.01); G06F 21/305 (2013.01); G06F 21/76 (2013.01);
Abstract

Embodiments are described for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller determines the status of the FPGA card debug port via a query to a management controller of the FPGA card. The remote access controller generates a passcode for the debug port and disables the debug port via a message to the management controller. The management controller detects a request, that includes a requestor password, for access to the debug port. The remote access controller authorizes the requestor's access to the debug port if the requestor password matches the generated passcode. The remote access controller disables the debug port upon each power cycle of the FPGA card or upon detecting removal of a device from the debug port.


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