The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Aug. 22, 2016
Applicant:

Hemlock Semiconductor Corporation, Hemlock, MI (US);

Inventors:

John Victor Bucci, Midland, MI (US);

Mark Richard Stachowiak, Midland, MI (US);

Charles Allan Stibitz, Midland, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/24 (2006.01); C23C 16/52 (2006.01); C23C 16/455 (2006.01);
U.S. Cl.
CPC ...
C23C 16/52 (2013.01); C23C 16/24 (2013.01); C23C 16/45512 (2013.01); C23C 16/45593 (2013.01);
Abstract

A method of improving polycrystalline silicon growth in a reactor, including: introducing a chlorosilane feed composition comprising trichlorosilane and dichlorosilane into a deposition chamber, wherein the deposition chamber contains a substrate; blending the chlorosilane feed composition with hydrogen gas to form a feed composition; adjusting a baseline flow of chlorosilane and hydrogen gas into the deposition chamber to achieve a pre-determined total flow and a pre-determined chlorosilane feed composition set point; applying pressure to the deposition chamber and energy to the substrate in the deposition chamber to form polycrystalline silicon; measuring the amount of dichlorosilane present in the chlorosilane feed composition and determining an offset value from a target value of dichlorosilane present in the chlorosilane feed composition; adjusting the chlorosilane feed composition set point by an amount inversely proportional to the dichlorosilane offset value; and depositing the formed polycrystalline silicon onto the substrate.


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