The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jan. 16, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Declan Carey, Cork, IE;

Frantz Stephane Florent Ngankem Ngankem, Cork, IE;

Pedro W. Neto, Munster, IE;

Ronan Casey, Cork, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H03M 1/667 (2013.01); H03K 19/017509 (2013.01); H03K 19/0175 (2013.01); H03M 1/66 (2013.01);
Abstract

Apparatus and associated methods relate to providing a regulation loop using a digital representation of a loop error signal along with a flexible multiplying capacitive digital-to-analog converter (MC-DAC) circuit to control one or more power switches (e.g., transistors) delivering required power (including voltage and/or current) to a load circuit. In an illustrative example, the MC-DAC circuit may include a digital-to-analog converter (DAC) configured to selectively couple to two different reference voltages in response to switch control signals generated by a digital filter. A capacitive level shifter may be coupled to the output of the DAC. A re-sampling circuit may be coupled to the output of the capacitive level shifter to generate a gate control signal to control the one or more power switches. The regulation loop may advantageously generate the gate control signal using a substantially reduced die area.


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