The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Aug. 20, 2018
Applicant:

University of Central Florida Research Foundation, Inc., Orlando, FL (US);

Inventors:

Seyed-Milad Tayebi, Orlando, FL (US);

Issa Batarseh, Orlando, FL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/44 (2007.01); H02M 1/14 (2006.01); H02M 7/44 (2006.01); H02M 3/04 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/44 (2013.01); H02M 1/14 (2013.01); H02M 1/143 (2013.01); H02M 7/44 (2013.01); H02J 2300/24 (2020.01); H02M 3/04 (2013.01); H02M 2001/007 (2013.01);
Abstract

A two-stage microinverter for coupling a PV panel to a power grid includes a DC/DC converter stage having an input for coupling to the PV panel and a DC/AC inverter stage that has an output for coupling to the grid, with at least one DC link capacitor between the DC/DC converter and DC/AC inverter stage. A synchronous controller that includes a loop compensator coupled to a mixer is between an analog-to-digital converter (ADC) and a phase-locked loop (PLL) for coupling to an output voltage from the grid. The ADC receives a DC link voltage from the DC link capacitor. An output of the PLL is for controlling a timing of sampling by the ADC of the DC link voltage so that the ADC samples the DC link voltage when an AC component of a ripple voltage on the DC link voltage intersects an average value of the DC link voltage.


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