The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jan. 30, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young Hwan Son, Hwaseong-si, KR;

Seo Goo Kang, Seoul, KR;

Shin Hwan Kang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 16/04 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11526 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01);
Abstract

A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.


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