The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Oct. 05, 2018
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Masao Kondo, Nagaokakyo, JP;

Masahiro Shibata, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 29/737 (2006.01); H01L 29/417 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H03F 3/21 (2006.01); H03F 1/30 (2006.01); H01L 29/06 (2006.01); H03F 3/213 (2006.01); H03F 3/195 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/49811 (2013.01); H01L 24/16 (2013.01); H01L 29/0649 (2013.01); H01L 29/41708 (2013.01); H01L 29/7371 (2013.01); H03F 1/302 (2013.01); H03F 3/195 (2013.01); H03F 3/21 (2013.01); H03F 3/213 (2013.01); H01L 24/13 (2013.01); H01L 2224/13147 (2013.01); H03F 2200/267 (2013.01); H03F 2200/451 (2013.01);
Abstract

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.


Find Patent Forward Citations

Loading…